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OKI Semiconductor
RA23
RA0
ROE RD7 RD0
BLOCK DIAGRAM
8-Bit LATCH 8 23-Bit Multiplexer 8 CPU interface DATA Controller PCM Synthesizer 16 8 PAN Register 16 x 9 MPY ADPCM Synthesizer 23-Bit Address Counter
D7/SD D6/SI D5/S0 S4/UD D3/SR3 D2/SR2 D1/SR1 D0/SR0 RCS CS WR RD CMD SERIAL NCR/BUSY
TEST1 TEST2 TEST3 TEST4
XT OSC Timing Controller
Digital Filter 14-Bit DAC
Digital Filter 14-Bit DAC
XT
OP Amplifier
OP Amplifier
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MSM9810B
RESET
DVDD DGND
LDAO AVDD AGND RDAO
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PIN CONFIGURATION (TOP VIEW)
64 RA23 63 RA22
62 RA21 61 RA20
60 RA0 59 RA17
58 RA16 57 RA15
56 RA14
55 RA13
54 RA12 53 RA11
52 RA10 51 RA9
DGND 1 AGND 2 TEST4 3 LDAO 4 RDAO 5 AVDD 6 DVDD 7 RCS 8 TEST1 TEST2 XT XT
9 10 11 12
50 RA19 49 RA18 48 DVDD 47 RA8 46 RA7 45 RA6 44 RA5 43 RA4 42 RA3 41 RA2 40 RA1 39 ROE 38 RD0 37 RD1 36 RD2 35 RD3 34 RD4 33 RD5
TEST3 13 SERIAL 14 CMD 15 RD 16 NC 17 WR 18 NCR/BUSY 19 CS 20 D0/SR0 21 D1/SR1 22 D2/SR2 23 D3/SR3 24 D4/UD 25 D5/SO 26 D6/SI 27 D7/SD 28 RESET 29 RD7 30 RD6 31 DGND 32
NC: No connection
64-pin Plastic QFP
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PIN DESCRIPTIONS
Pin 40-47, 49-64 Symbol RA23-RA0 Type O Description Address pins for external memory. These pins become high impedance when RCS pin is "H". Data pin for external memory. Pull-down resistors are internally connected to these pins. These pull-down resistors become valid when the RCS pin is "H", and become invalid when the RCS pin is "L". Output enable pin for external memory. When this pin is "L", RA23 to RA0 and ROE pins output address data and output enable signal. When this pin is "H", RA23 to RA0 and ROE pins become high impedance. Select pin for Command data or Subcommand data for CPU interface. When this pin is "H", subcommand input is selected. When this pin is "L", command input is selected. A pull-up resistor is internally connected to this pin. Read pin for CPU interface. A pull-up resistor is internally connected to this pin. Write pin for CPU interface. A pull-up resistor is internally connected to this pin. Chip select pin for CPU interface. When CS is "H", WR/RD signal is not entered in this LSI. A pull-up resistor is internally connected to this pin. CPU input interface select pin. When SERIAL is "H", serial input interface is selected. When it is "L", parallel input interface is selected. Data bus pin for CPU interface when parallel input interface is selected. When WR is "L", this pin serves as data input pin. 28 D7/SD I/O When RD is "L", this pin serves as channel status data output pin. When serial input interface is selected, this pin serves as serial data input pin. Data bus pin for CPU interface when parallel input interface is selected. When WR is "L", this pin serves as data input pin. 27 D6/SI I/O When RD is "L", this pin serves as channel status output pin. When serial input interface is selected, this pin serves as serial clock input pin. Data bus pin for CPU interface when parallel input interface is selected. When WR is "L", this pin serves as data input pin. 26 D5/SO I/O When RD is "L", this pin serves as channel status output pin. When serial input interface is selected, this pin serves as channel status serial output pin.
30, 31, 33-38 39
RD7-RD0 ROE RCS
I O
8
I
15
CMD
I
16 18 20
RD WR CS
I I I
14
SERIAL
I
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Pin
Symbol
Type
Description Data bus pin for CPU interface when parallel input interface is selected. When WR is "L", this pin serves as data input pin. When RD is "L", this pin serves as channel status output pin. When serial input interface is selected, this pin serves as channel status select pin. When UD is "H", channels 8 thru 5 are output to SR3 thru SR0, respectively. When UD is "L", channels 4 thru 1 are output to SR3 thru SR0, respectively.
25
D4/UD
I/O
24 23 22 21 4 5 11
D3/SR3 D2/SR2 I/O D1/SR1 D0/SR0 LDAO RDAO XT O O I
Data bus pin for CPU interface when parallel input interface is selected. When WR is "L", this pin serves as data input pin. When RD is "L", this pin serves as channel status output pin. When serial input interface is selected, this pin serves as channel status output pin. When UD is "H", channels 8 thru 5 are output to SR3 thru SR0, respectively. When UD is "L", channels 4 thru 1 are output to SR3 thru SR0, respectively. LEFT side analog output pin. RIGHT side analog output pin. Crystal or ceramic oscillator connection pin. A feedback resistor of about 1M is connected between XT and XT. When external clocks are used, enter external clocks into this pin. Crystal or ceramic oscillator connection pin. When external clocks are used, leave this pin open. When this pin is "L" level, the LSI is initialized. At that time, oscillation stops and D/A outputs go to GND level. A pull-up resistor is internally connected to this pin. Channel status select pin. When this pin is "H", NCR signal is output. When it is "L", BUSY signal is output.
12
XT RESET
O
29
I
19 9 10 13 3 6 7, 48 2 1, 32
NCR/BUSY TEST1 TEST2 TEST3 TEST4 AVDD DVDD AGND DGND
I
I
Pins for LSI testing. Apply "L" level to these pins.
-- -- -- --
Analog power supply pin. A bypass capacitor of 01 F or more should be connected between the AGND pin and the AVDD pin. Digital power supply pin. A bypass capacitor of 0.1 F or more should be connected between the DGND pin and the DVDD pin. Analog GND pin. Digital GND pin.
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ABSOLUTE MAXIMUM RATINGS
(GND = 0 V) Parameter Power Supply Voltage Input Voltage Storage Temperature Symbol VDD VIN TSTG Condition Ta= 25C -- Rating -0.3 to +7.0 -0.3 to VDD+ 0.3 -55 to +150 Unit V V C
RECOMMENDED OPERATING CONDITIONS
(GND = 0 V) Parameter Power Supply Voltage Operating Temperature Master Clock Frequency Symbol VDD Top fOSC Condition -- -- -- Min. 3.5 Range 4.5 to 5.5 -40 to +85 Typ. 4.096 Max. 4.5 Unit V C MHz
ELECTRICAL CHARACTERISTICS
DC Characteristics
(DVDD = AVDD = 4.5 to 5.5 V, DGND = AGND = 0 V, Ta = -40 to +85C) Parameter High-level Input Voltage Low-level Input Voltage High-level Output Voltage Low-level Output Voltage High-level Input Current 1 High-level Input Current 2 (Note 1) Low-level Input Current 1 Low-level Input Current 2 (Note 2) Output Leakage Current Operating Current Standby Current Symbol VIH VIL VOH VOL IIH1 IIH2 IIL1 IIL2 ILO IDD IDS Condition -- -- IOH = -1 mA IOL = 2 mA VIH = VDD Applied to pins with internal pull-down resistor VIL = GND Applied to pins with internal pull-up resistor 0 VOUT VDD fOSC 4 MHz, no load Ta = -40 to +70C Ta = +70 to +85C Min. 0.84 x VDD -- VDD - 0.4 -- -- 30 -10 -300 -10 -- -- -- Typ. -- -- -- -- -- -- -- -- -- 6 -- -- Max. -- 0.16 x VDD -- 0.4 10 300 -- -30 +10 15 15 50 Unit V V V V A A A A A mA A A
Notes
1: 2:
Applicable to RD7 to RD0 pins (when RCS = "H"). Applicable to CMD, RD, WR, and CS pins.
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Analog Characteristics
(DVDD = AVDD = 4.5 to 5.5 V, DGND = AGND = 0 V, Ta = -40 to +85C) Parameter LDAO,RDAO Output Load (During OP amplifier output) LDAO,RDAO Output Impedance (When OP amplifier is not used) LDAO,RDAO Output Level Symbol ROUTA ROUTD -- Condition -- -- No load Min. 50 -- -- Typ. -- 3 0.7 to 0.94 x VDD Max. -- -- -- Unit k k V
AC Characteristics
(VDD = 4.5 to 5.5 V, GND = 0 V, Ta = -40 to +85C, CL = 5 pF) Parameter Master Clock Duty Cycle RESET Input Pulse Width RESET Input Time From Raising of Power Supply Set up and Hold Time of CS for RD RD Pulse Width Output Data Valid Time after Fall of RD Data Float Time after Rise of RD Setup and Hold Time of CMD for WR Setup and Hold Time of CS for WR WR Pulse Width Data Setup Time before Rise of WR Data Hold Time after Rise of WR WR - WR Pulse Interval CS - CS Pulse Interval Serial Data Setup Time Serial Data Hold Time Serial Clock Pulse Width Output Data Valid Time after Rise of Serial Clock Setup Time of WR for Serial Data Setup Time of Serial Clock Fall for WR Rise Setup Time of RD for Serial Clock Rise Symbol fduty tW(RST) tD(RST) tCR tRR tDRE tDRF tDW tCW tWW tDWS tDWH tWWS tCC tSDS tSSD tW(SCK) tSDD tSWDS tSIWS tSRIS Min. 40 1 0 30 200 -- -- 50 30 200 100 30 160 100 30 30 200 -- 200 300 300 Typ. 50 -- -- -- -- -- 10 -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 60 -- -- -- -- 100 50 -- -- -- -- -- -- -- -- -- -- 200 -- -- -- Unit % s s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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TIMING DIAGRAMS (Parallel Input)
Data Read Timing
CS(I)
VIH VIL
tCR RD(I)
VIH VIL
tCR
tRR
VOH
D7 - D0(O)
VOL
Data out Valid tDRE tDRF
Data Write Timing (Sub-command, Command Input)
CMD(I)
VIH VIL
tDW
tDW tDW tDW
CS(I)
VIH VIL
tCC tCW
tCW
WR(I)
VIH VIL
tWSS
VIH
tWW Data Stable tDWS tDWH
D7 - D0(I)
Data Stable
VIL
tDWS
tDWH
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TIMING DIAGRAMS (Serial Input)
Data Write Timing (Sub-command, Command Input)
VIH
tDW tDW tDW tCC
tDW
CMD(I)
VIL
VIH
CS(I)
VIL
tCW
VIH
tCW
WR(I)
VIL
tWSS
SD(I) tSWDS tSIWS tSIWS
SI(I)
VIH
WR(I)
VIL
tSWDS
VIH
SD(I)
VIL
tSDS
VIH
tSSD tW(SCK) tW(SCK)
tSDS tW(SCK)
tSSD tW(SCK)
SI(I)
VIL
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Data Read Timing
CS(I)
VIH VIL
tCR RD(I)
VIH VIL
tCR
SO(O)
D7 D6
D5 D4 D3 D2
D1
D0
SI(I)
RD(I)
VIH VIL
SO(O)
VOH VOL
tSRIS SI(I)
VIH VIL
tSDD
tSDD
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TIMING DIAGRAM (Common to Parallel and Serial I/O)
Power-on Timing * Power-down Timing
4.5 V
VDD tD(RST)
VIH VIL
RESET (I)
tW(RST)
XT XT
Oscillating
Reset processing
Oscillation stabilization time
Waiting for command
Standby
LDAO (O)
1/2VDD
GND
1/2VDD
RDAO (O)
1/2VDD
GND
1/2VDD
XT XT
Oscillating
Oscillating
RESET (I)
tW(RST)
Waiting for command
Standby
Oscillation stabilization time
Waiting for command
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Continuous Playback Timing When Phrase Control Table is not Used
FADR(2) playback
FADR(1) playback
LDAO/RDAO
FADR1
START
FADR2
START
Sub-command/Command
NCRn
BUSYn
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FADR(1) playback
FADR(2) playback
LDAO/RDAO
FADR1 FADR2
START
START
Sub-command/ Command Note)
Continuous Playback Timing When Phrase Control Table is Used
NCRn
BUSYn
FEDL9810BFULL-03
(Note) Do not enter the START command and MUON command during playback (BUSY = "L") when the phrase control table is used. Otherwise, the LSI may malfunction. Enter the START command and MUON command after BUSY = "H".
MSM9810B
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FADR(1) playback
FADR(1) playback LOOP valid
FADR(1) playback LOOP valid
LDAO/RDAO
LOOP Playback Timing (Phrase Table is Used/not Used)
Sub-command/ Command
FADR1
START
LOOP set
LOOP released
NCRn
BUSYn
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FADR(1) playback
Silence (4 to 1020 ms) MUON command FADR(2) playback
DAOL/ DAOR START
Sub-command/ Command
FADR1
START
MUON
FADR2
NCRn
MUON Command Input Timing When Phrase Control Table is not Used
BUSYn
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FADR(1) playback Silence (4 to 1020 ms) MUON command
FADR(2) playback
DAOL/DAOR
Sub-command/ Command Note) Note)
FADR1 FADR2
START
MUON
START
MUON Command Input Timing When Phrase Control Table is Used
NCRn
BUSYn
(Note) Do not enter the START command and MUON command during playback (BUSY = "L") when the phrase control table is used. Otherwise, the LSI may malfunction. Enter the START command and MUON command after BUSY = "H". MSM9810B
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FUNCTIONAL DESCRIPTION
Microcontroller Interface The microcontroller interface includes two interface circuits, parallel interface and serial interface. The statuses of each pin both in parallel interface mode and in serial interface mode are shown below.
SERIAL = "L" Parallel I/O interface D7 (I/O) D6 (I/O) D5 (I/O) D4 (I/O) D3 (I/O) Data I/O pins D2 (I/O) D1 (I/O) D0 (I/O) SR2 (O) SR1 (O) SR0 (O) SD (I) SI (I) SO (O) UD (I) SR3 (O)
SERIAL = "H" Serial I/O interface Serial data input pin Serial clock input pin Serial data output pin Select pin for channel statuses output via SR3 to SR0 Channel 1 is output when UD is 0 and channel 5 when UD is 1. Channel 2 is output when UD is 0 and channel 6 when UD is 1. Channel 3 is output when UD is 0 and channel 7 when UD is 1. Channel 4 is output when UD is 0 and channel 8 when UD is 1.
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Command List Commands Each command consists of a command and a sub-command. The sub-command is input when the CMD pin is "H". The command is input when the CMD pin is "L".
NCRn Valid only at "H" None Command CMD pin name START H L STOP H L None LOOP H L None Valid only at "H" OPT H L H MUON L H None FADR L H H H H H H H 0 0 1 0 0 1 0 0 C2 to C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D7 to D0 7 6 5 4 3 2 1 0 Description Sets the bit of a voice synthesis start channel to "1". Starts playback. Sets the bit of a voice synthesis end channel to "1". Ends playback. Sets the bit of a LOOP channel to "1". Starts LOOP.
CH8 to CH1 0 0 X X X
CH8 to CH1 0 1 X X X
CH8 to CH1 1 O4 1 0 X X O1 X X
O3 O2 1 X
O0 Selects an option. X Selects a silence time at M x 4 ms. (Condition: 1 M 255) Selects a channel that outputs a silence and plays a silence. Selects a phrase to be played. Selects a channel that sets up a phrase. Selects a ROM address at which voice synthesis starts. Selects a ROM address at which voice synthesis ends. Selects a sampling frequency using S3 to S0. Selects a voice synthesis method using P1 to P0. Sets the condition to a channel selected by C2 to C0. Sets a playback volume between V3 and V0 x -2 dB. Selects a channel to which a playback volume is set. Selects a left side voice volume using L3 to L0 and selects a right side voice volume using R3 to R0. The volume of output is -2 dB x (L or R). Selects a channel for setting PAN using C2 to C0.
M7 to M0
FA7 to FA0 0 1 C2 to C0
None
DADR
SA23 to SA16 SA15 to SA8 SA7 to SA0 ST23 to ST16 ST15 to ST8 ST7 to ST0 S3 to S0 P1 to P0 1 X 1 1 0 0 0 0
L H None CVOL L
0 X 0
0 X 0
1 X 1
CH1 to CH0
V3 to V0 C2 to C0
H None PAN L X: Don't Care 0
L3 to L0
R3 to R0
1
0
0
0
C2 to C0
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Sampling Frequency List
S3 to S0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Sampling Frequency 4.0 kHz 8.0 kHz 16.0 kHz 32.0 kHz Undefined 6.4 kHz 12.8 kHz 25.6 kHz Undefined 5.3 kHz 10.6 kHz 21.2 kHz Undefined Undefined Undefined Undefined
Voice Synthesis Algorithm List
P1 to P0 0 1 2 3 Voice synthesis algorithm OKI 4-bit ADPCM OKI 4-bit ADPCM2 8-bit Straight PCM OKI 8-bit Nonlinear PCM
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PAN and CVOL List
L3 to L0 R3 to R0 V3 to V0 0 1 2 3 4 5 6 7 0 dB -2 dB -4 dB -6 dB -8 dB -10 dB -12 dB -14 dB Volume
L3 to L0 R3 to R0 V3 to V0 8 9 10 11 12 13 14 15 -16 dB -18 dB -20 dB -22 dB -24 dB -26 dB -28 dB -30 dB Volume
OPT Command List
Default * O4 0 0 1 1 * x x x * x x O3 0 1 0 1 x x x x x O2 x x x x 0 0 1 x x O1 x x x x 0 1 x x x O0 x x x x x x x 0 1 Description Sets the volumes of all channels to VDD (p-p). Sets the volumes of all channels to 1/2 VDD (p-p). Sets the volumes of all channels to 1/4 VDD (p-p). Sets the volumes of all channels to 1/8 VDD (p-p). Secondary digital filtering is performed. Primary digital filtering is performed. An on-chip digital filter is not used. Data is output directly from a D/A converter. (Output Z 3 k) Data is output via an OP amplifier. (Output Z 500 )
(Note) x indicates that data is independent of a function described.
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LPF Frequency Characteristics This LSI contains a LPF in which a digital filter technology is used. The frequency characteristics when a secondary filter is used at fs = 8 kHz is shown below. The cutoff frequency is directly proportional to the sampling frequency fs.
[dB]
0 -10 -20 -30 -40 -50 -60 -70 -80 -90
-100 100
1000
10000
100000 [Hz]
LPF Output Frequency Characteristics (fs = 8 kHz)
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Power Down Function To enter the power down mode, set the RESET pin to "L". When an external clock is supplied to the XT pin, fix the XT pin at "L". If an external clock is supplied via the XT pin during the power down mode, the IDS specification is not satisfied because current flows between the XT pin and the XT pin. The circuit of XT and XT pins is shown below.
Internal master clock Approx. 500 k
RESET Power down mode "L"
XT "L"
XT
Channel Status The channel status includes NCRn and BUSYn. These two channel statuses can be switched by setting the NCR/BUSY pin.
Corresponding channel CH1 CH2 CH3 CH4
NCR/BUSY = "H" NCR1 NCR2 NCR3 NCR4
NCR/BUSY = "L" BUSY1 BUSY2 BUSY3 BUSY4
The n-channel NCR signal is NCRn and the n-channel BUSY signal is BUSYn. When NCRn is "H", the START command and MUON command can be input for the next message of "n" channel to be played. When the phrase control table is used and BUSYn is "L", do not enter the START command and MUON command even if NCRn is "H". Otherwise, the LSI may malfunction. When BUSYn is "H", the "n" channel does not output a voice. When BUSYn is "L", the "n" channel outputs a voice.
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Parallel I/O (SERIAL = "L") The outputs of channel statuses in parallel I/O mode are shown below.
Pin name D3 D2 D1 D0 NCR/BUSY = "H" NCR4 NCR3 NCR2 NCR1 NCR/BUSY = "L" BUSY4 BUSY3 BUSY2 BUSY1
Serial I/O (SERIAL = "H") The outputs when channel statuses are serially read during serial I/O mode are shown below.
Signal name SO7 SO6 SO5 SO4 SO3 SO2 SO1 SO0 NCR/BUSY = "H" NCR8 NCR7 NCR6 NCR5 NCR4 NCR3 NCR2 NCR1 NCR/BUSY = "L" BUSY8 BUSY7 BUSY6 BUSY5 BUSY4 BUSY3 BUSY2 BUSY1
The outputs when channel statuses are output via SR3 to SR0 during serial I/O mode are shown below.
UD = "L" Pin name SR3 SR2 SR1 SR0 NCR/BUSY = "H" NCR4 NCR3 NCR2 NCR1 NCR/BUSY = "L" BUSY4 BUSY3 BUSY2 BUSY1 UD = "H" NCR/BUSY = "H" NCR8 NCR7 NCR6 NCR5 NCR/BUSY = "L" BUSY8 BUSY7 BUSY6 BUSY5
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Voice Synthesis Algorithms The MSM9810B contains 4-bit ADPCM algorithm, 4-bit ADPCM2 algorithm, 8-bit straight PCM algorithm, and 8-bit non-linear PCM algorithm. One of these algorithms can be selected depending on the kind of voices to be played. The features of these algorithms are described below.
Voice synthesis algorithm Oki 4-bit ADPCM Oki 4-bit ADPCM2 Applicable waveform Normal voice waveforms Normal voice waveforms Sound effects including high frequency components Sound effects including high frequency components Feature Oki-original 4-bit ADPCM An improved version of Oki-original 4-bit ADPCM. This algorithm has improved its waveform traceability. This algorithm plays back the center of waveform as a 10-bit sound. Normal 8-bit PCM algorithm
Oki 8-bit Nonlinear PCM 8-bit PCM
Memory Configuration and Voice Data Creation Method The ROM data consists of a voice management area, a voice data area, and a phrase control table area. The voice management area controls the voice data start address, voice data end address, and use of the phrase control table. 256 phrases of voice management data are stored in this area. The voice data area stores actual waveform data. The phrase control table area stores data for effectively using voice data. See "Phrase Control Table Function" for details. The ROM data is created by using a dedicated tool.
ROM address 0x000000 0x0007FF 0x000800 Voice management area (16 Kbit fixed)
Voice data area
max: 0x7ffffff Phrase control table area max: 0x7ffffff This area is used to create ROM data.
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Playback Time and Memory Capacity The playback time is determined by external memory capacity, sampling frequency, and voice synthesis algorithm. The relationship is described below.
1.024 x (Memory capacity - 16) (Kbits) Playback time = Sampling frequency (kHz) x bit length (Seconds) (The bit length is 4 bits for ADPCM and ADPCM2 and 8 bits for PCM.)
When the sampling frequency is 16 kHz and the voice synthesis algorithm is 4-bit ADPCM and an 8-Mbit ROM is used, the playback time is calculated as shown below.
Playback time = 1.024 x (8192 - 16) (Kbits) 16 (kHz ) x 4 (bit) 131 (Seconds)
In the above equation, the playback time when the phrase control table function is not used is shown.
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Mixing Function It is possible to mix eight channels at a time. Moreover, the LSI is capable of starting or stopping voices of each channel separately. * Note on waveform clamping during mixing Increasing the number of channels to be mixed may cause clamping. To prevent clamping, reduce the volumes of all channels using the OPT command. (Note) Mixing using a different sampling frequency cannot be done.
Continuous Playback Function The continuous playback function is used to continuously play back the next phrase after playing back a phrase. The next phrase to be played can be previously selected while a phrase is being played back. See "Continuous Playback Flowchart" for details. The continuous playback function is also available in the case of the phase control table. (Note) The following changes of voice synthesis algorithms are not permitted for continuous playback function. These changes may generate noises. * ADPCM ADPCM2 * ADPCM2 ADPCM
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Phrase Control Table Function The phrase control table function is used to continuously play back multiple phrases. It is possible to perform the following functions using the phrase control table function. * Continuous playback (The number of continuous playbacks can be specified limitlessly, but depends on memory capacity.) * Silence insertion function (4 mSec to 124 mSec) The memory capacity of voice ROM is effectively used by using the phrase control table function. Examples of ROM data when the phrase control table function is used are shown below. Example 1) Phrases when the phrase control table function is used
Phrase 1 Phrase 2 Phrase 3 Phrase 4 Phrase 5 It It It It It is is is is is fine rainy fine rainy fine today today tomorrow tomorrow today Silence It is rainy tomorrow
Example 2) ROM data when the example 1 is converted into ROM
Address management area It fine is rainy today tomorrow Phrase control area
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Volume Function A volume can be adjusted at the stages of OPT, CVOL and PAN as shown below. * A volume is set to all channels at the stage of OPT. * A volume is set to each channel at the stage of CVOL. * A volume is set to "L" and "R" of each channel at the stage of PAN.
CH1 CVOL
PAN[L] PAN[R] Left-side Mixing Block
CH2 CVOL ADPCM Block OPT CH3 CVOL
PAN[L] PAN[R] PAN[L] PAN[R]
Left-side Output
CH4 CVOL
PAN[L] PAN[R]
Rightside Mixing Block
Rightside Output
CH5 CVOL
PAN[L] PAN[R]
CH6 CVOL
PAN[L] PAN[R]
CH7 CVOL
PAN[L] PAN[R]
CH8 CVOL
PAN[L] PAN[R]
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The output level attenuations when the CVOL, OPT and PAN commands are executed are shown below. Left-side output volume = (V + L) x -2 + (O4 x 2 + O3) x -6 [dB] V: Setting a volume (0 to 15) with the CVOL command L: Setting a left-side volume (0 to 15) with the PAN command O4, O3: Setting a volume (0 or 1) with the OPT command Right-side output volume = (V + L) x -2 + (O4 x 2 + O3) x -6 [dB] V: Setting a volume (0 to 15) with the CVOL command L: Setting a right-side volume (0 to 15) with the PAN command O4, O3: Setting a volume (0 or 1) with the OPT command
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MSM9810B
COMMAND FUNCTIONS
START Command The START command starts voice synthesis of the channel corresponding to the data stored in the TMP register. Table 1 shows the correspondence between data input (D7-D0) and channels. In the case of serial input, all 8 bits of D7 to D0 should be input serially from MSB. Table 1 Correspondence between D7-D0 and Channels
Data bus Corresponding channel D7 CH8 D6 CH7 D5 CH6 D4 CH5 D3 CH4 D2 CH3 D1 CH2 D0 CH1
When the START command is input, data stored in the TMP register is set at the start register, and voice synthesis processing starts. For example, when all "1" is written from the data bus to the TMP register and the START command is input, all channels start voice synthesis simultaneously. Input the START command when the status signal (NCR or BUSY) of the channel to be started is at "H". When NCR is "L", input is disabled. When the phrase control table is used, input the START command while BUSY is "H". Otherwise, the LSI may malfunction. Figure 4 shows the flowchart when the START command is input.
RD pulse input NO
NCRn corresponding to each channel is output to D7-D0 Check that D7-D0 corresponding to the channel to start voice synthesis is "H". (BUSYn is "H" when the phrase control table is used) After setting "L" to D7-D0 corresponding to the channel to start voice synthesis from the data bus, input the WR pulse. (Set CMD to "H".)
NCRn="H" YES Subcommand input START command input
Figure 4 START Command Input Flow STOP Command The STOP command stops voice synthesis processing of the channel corresponding to data stored in the TMP register. Table 2 shows the correspondence between data input (D7-D0) and channels. Table 2 Correspondence between D7-D0 and channels
Data bus Corresponding channel D7 CH8 D6 CH7 D5 CH6 D4 CH5 D3 CH4 D2 CH3 D1 CH2 D0 CH1
When the STOP command is input, the LSI stops processing of voice synthesis of the corresponding channel at the rise of the WR pulse. When voice synthesis stops, the PCM value of that channel is cleared to 1/2 VDD, and the NCR and BUSY channel status signals become "H". When "H" has been set at the START register, the START register is cleared to "L".
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LOOP Command The LOOP command repeats a playback of voice synthesis of the channel corresponding to data stored in the TMP registers. Table 3 shows the correspondence between data input (D7-D0) and channels. Table 3 Correspondence between D7-D0 and Channels
Data bus Corresponding channel D7 CH8 D6 CH7 D5 CH6 D4 CH5 D3 CH4 D2 CH3 D1 CH2 D0 CH1
When the LOOP command is input, the LSI writes data of the TMP register to the LOOP register at rise of WR pulse, and repeats a playback of the channel where "H" is set. Once "H" is set at the LOOP register, playback continues until "L" is set from the outside. If the phrase control table function has been used for a phrase address, the edited voice is repeatedly played back. To end a repeating playback, set the register of the channel to end the repeat to "L" using the LOOP command again. When the register is set to "L", repeating ends with the phrase next to the current playback phrase. If the START register has been set to continue the playback of another phrase, another phrase is played back continuously after repeating ends. Figure 5 shows an example.
Channel 1 Phrase 1 Phrase 1 Phrase 1 Phrase 1 Phrase 2
Phrase 1 LOOP start start
LOOP end
Phrase 2 start
Figure 5 LOOP Command Execution Example
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OPT Command The OPT command changes the setting inside the LSI according to data stored in the TMP register. Table 4 shows the correspondence between data input (D7 to D0) and options. (Input "L" to D7-D5.) Table 4 OPT Command List
Default * O4 0 0 1 1 * x x x * x x O3 0 1 0 1 x x x x x O2 x x x x 0 0 1 x x O1 x x x x 0 1 x x x O0 x x x x x x x 0 1 Description Sets the volumes of all channels to VDD (p-p). Sets the volumes of all channels to 1/2 VDD (p-p). Sets the volumes of all channels to 1/4 VDD (p-p). Sets the volumes of all channels to 1/8 VDD (p-p). Secondary digital filtering is performed. Primary digital filtering is performed. An on-chip digital filter is not used. Data is output directly from a D/A converter. (Output Z 3 k) Data is output via a voltage follower. (Output Z 500 )
(Note) x indicates that data is independent of a function described. When the OPT command is input, the LSI changes the option at the rising edge of the WR pulse. When power is turned on, or when the RESET pulse is input, the registers corresponding to D4-D0 have been set to "L". If the option is changed when voice synthesis is in execution, voice quality may change. Oki recommends to set the option after power is turned on or after RESET is input. 1) Volume Option Volume can be set by the CVOL command and PAN command, but a waveform may be clamped when channel synthesis is executed. If the CVOL command and PAN command are used to prevent a waveform from being clamped, the number of steps used for actual volume decreases, and effective voice synthesis may not be performed. If it is known that a waveform will be clamped, this option can set the volume of all channels to low, so that the number of steps of the volume can be utilized to the maximum level. 2) Digital Filter Processing This LSI has a built-in oversampling circuit for digital filter processing. This oversampling system evenly generates four times more points of sampling frequencies. When power is turned on or if the RESET pulse is input, those pulses have been set to pass through the oversampling circuit. If digital filter processing is unnecessary, change this setting by the OPT command.
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3) Analog Output When power is turned on, it has been set that the output of the D/A converter is directly output. To change this setting, use the OPT command. The output impedance of analog signals being output via the voltage follower is about 500 . The output impedance of analog signals directly output from the D/A converter is about 3 k. MUON Command The MUON command inserts silence into the specified channel at the rise of the WR pulse. The length of silence is according to the size of data stored in the TMP register. The length of silence data is input in advance, before executing the MUON command. Silence length can be set for 255 steps, 4 ms to 1020 ms, in 4 ms intervals. Silence time can be set as follows. tmu = (27 x (D7) + 26 x (D6) + 25 x (D5) + 24 x (D4) + 23 x (D3) + 22 x (D2) + 21 x (D1) + 20 x (D0)) x 4.096 ms The operation of the MUON command is similar to the START command to start voice synthesis. When the MUON command is input, "H" is set to the START register, and NCR and BUSY signals become "L". If the MUON command is input when voice synthesis is in execution, silence time is inserted after voice synthesis ends. Input the MUON command when the status signal (NCR or BUSY) of the channel to start voice synthesis is at "H". When NCR is "L", input is disabled. When the phrase control table is used, input the MUON command while BUSY is "H". Otherwise, the LSI may malfunction. Figure 6 shows a flow chart example when the MUON command is input.
RD pulse input NO
NCRn corresponding to each channel is output to D7-D0. Check that D7-D0 corresponding to the channel to insert silence is "H". (BUSYn is "H" when the phrase control table is used) After setting time of inserting silence from the data bus, input WR pulse (set CMD to "H"). Specify channel by MUON command.
NCRn = "H" YES Subcommand input MUON command input
Figure 6 MUON Command Input Flow
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FADR Command The FADR command transfers data stored in the TMP register to the phrase address register of the corresponding channel at the rise of the WR pulse. For the phrase address, the user specification phrases have been set by an analysis tool, and the playback system, sampling frequency and start and stop address of voice data have been registered to the address management area. When the phrase address is set and the START command is input, the LSI reads data of the address management area, and starts voice synthesis. Since the phrase address is set by D7-D0, a maximum of 256 phrases can be set. The edit function can be used for phrase addresses, so not only one phrase but combinations with other phrases are possible. DADR Command The DADR command transfers data stored in the TMP (1-7) register to the start and stop address register of the corresponding channel at the rise of the WR pulse. For the direct address, the playback system, sampling frequency, and start and stop addresses of voice data are directly input from the microcomputer without using the address management area. Direct address playback system is available with channel 1 to 4, and not available with channel 5 to 8. Since the phrase that can be set at a phrase address is a maximum of 256, if voice data exceeds 256 phrases, use this command. Data on the playback system, sampling frequency, and start and stop address of voice data is displayed when an analysis tool is used. Data on the playback system, sampling frequency, and start and stop address of voice data is input to the TMP1 to TMP7 registers divided in 7 steps, unlike the data input of other commands. Figure 7 shows the input method.
CMD(I)
CS(I)
WR(I)
D7-D0(I) Stores TMP1 register data Stores TMP3 register data Stores TMP5 register data Stores TMP7 register data Executes command
Stores TMP2 register data
Stores TMP4 register data
Stores TMP6 register data
Figure 7 DADR Input Timing
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As Figure 7 shows, CS and WR pulses are input 7 times when CMD is in "H" status, to input data to the TMP1 to TMP7 registers. The LSI increments the registers at the rise of the WR pulse when CMD is "H". CMD must not be "L" while inputting data. When CMD becomes "L" while inputting data, a normal setting cannot be made. Table 5 shows the configuration of data to be input to TMP1 to TMP7 registers. Table 5 TMP Register Data Configuration
D7 TMP1 register TMP2 register TMP3 register TMP4 register TMP5 register TMP6 register TMP7 register A23 A15 A7 T23 T15 T7 S3 D6 A22 A14 A6 T22 T14 T6 S2 D5 A21 A13 A5 T21 T13 T5 S1 D4 A20 A12 A4 T20 T12 T4 S0 D3 A19 A11 A3 T19 T11 T3 P1 D2 A18 A10 A2 T18 T10 T2 P0 D1 A17 A9 A1 T17 T9 T1 0 D0 A16 A8 A0 T16 T8 T0 0
Input the start address of voice data to TMP1 to TMP3 registers. Input the stop address of voice data to TMP4 to TMP6 registers. Input the playback system and sampling frequency to the TMP7 register. Table 6 shows the input data configuration of the playback system and sampling frequency. Table 6 Data Configuration of Playback System and Sampling Frequency
S3 0 0 0 0 0 0 0 1 1 1 P1 0 0 1 1 S2 0 0 0 0 1 1 1 0 0 0 S1 0 0 1 1 0 1 1 0 1 1 P0 0 1 0 1 Playback algorithm: 4-bit ADPCM Playback algorithm: 4-bit ADPCM2 Playback algorithm: 8-bit straight PCM Playback algorithm: 8-bit non-linear PCM S0 0 1 0 1 1 0 1 1 0 1 Sampling frequency 4.0 kHz Sampling frequency 8.0 kHz Sampling frequency 16.0 kHz Sampling frequency 32.0 kHz Sampling frequency 6.4 kHz Sampling frequency 12.8 kHz Sampling frequency 25.6 kHz Sampling frequency 5.3 kHz Sampling frequency 10.6 kHz Sampling frequency 21.3 kHz
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CVOL Command The CVOL command adjusts the volume of the specified channel to the volume which corresponds to the size of data stored in the TMP register at the rise of the WR pulse. Volume can be set in 16 steps up to -30 dB in -2dB step units. Set data as shown in Table 7.
Table 7 Volume Setting Data Configuration
D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Volume(dB) 0 dB -2 dB -4 dB -6 dB -8 dB -10 dB -12 dB -14 dB -16 dB -18 dB -20 dB -22 dB -24 dB -26 dB -28 dB -30 dB
(D7-D4: Don't care) When power is turned on and the RESET pulse is input, all channels are set to 0 dB.
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PAN Command The PAN command adjusts the volume of the specified channel for the left and right respectively, to the volume which corresponds to the size of data stored in the TMP register at the rise of the WR pulse. This command enables stereo output. When volume is controlled by the OPT command and CVOL command, volume to be output is the volume stored in ROM multiplied by volume set by the OPT command, CVOL command, and PAN command respectively. This volume is output from LDAO and RDAO. Volume can be set in 16 steps up to -30 dB in -2 dB step units. Set data as shown in Table 8.
Table 8 PAN Data Configuration
D7 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D6 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D5 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D4 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Volume at left side Volume at right side 0 dB -2 dB -4 dB -6 dB -8 dB -10 dB -12 dB -14 dB -16 dB -18 dB -20 dB -22 dB -24 dB -26 dB -28 dB -30 dB
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FLOWCHART
Monaural Playback
Start monaural playback.
Select a phrase to start voice synthesis. (FADR command)
Set up a volume for each channel. (CVOL command)
Set up PAN for each channel. (PAN command)
Yes Do mixing with other channels?
No
Select a channel to start playback. (START command)
End playback?
Select a channel to end playback. (STOP command)
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Stereo Playback
Start stereo playback.
Select a phrase of a left side channel. (FADR command)
Select a phrase of a right side channel. (FADR command)
Set up PAN of a left side channel. (PAN command)
Set up PAN of a right side channel. (PAN command)
Yes Do mixing with other channels?
No Start playback. (START command)
End playback?
Select a channel to end playback. (STOP command)
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Continuous Playback
Start continuous playback.
Select a phrase to start voice synthesis. (FADR command)
Set up PAN. (PAN command)
Start voice synthesis of the first phrase.
Set up CVOL. (CVOL command)
Select a channel to start playback. (START command)
No NCR = 1? Yes Select a phrase to be played next. (FADR command)
Is it possible to select a phrase to be played next?
Select a phrase to be played next.
Select a channel to start playback. (START command)
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Changing Volume Level It is possible to change the volume level of a channel that is being played. If the CVOL command is issued when voices are not being played, the changed volume level will be valid during the next playback. When the phrase control table function is used, the value of CVOL is changed by the phrase control table function because there are volume setting values in the phrase control table.
Voices are being played
(BUSY = 0)
Change the volume level of the selected channel? Yes
No
Change the volume level of the selected channel. CVOL command
Change PAN of the channel? Yes PAN command
No
Change the volume level of the selected channel.
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74HC139 Y3 Y2 2B Y1 2A Y0
MSM27C401CZ MSM27C401CZ MSM27C401CZ MSM27C401CZ
OKI Semiconductor
MCU M9810B RA20 RA19 CE 19 RA18-0 8 RD7-0 OE ROE OE OE D7-0 D7-0 D7-0 A18-0 A18-0 A18-0 A18-0 D7-0 OE CE CE CE
APPLICATION CIRCUITS
1G
2G
SD SI SO CMD CS WR RD RESET
SERIAL NCR/BUSY LDAO AMP
RCS TEST1 TEST2 TEST3 TEST4 RDAO AMP XT XT
FEDL9810BFULL-03
MSM9810B
Application circuit example when four 4 Mbit OPT ROMs are connected (serial input interface)
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PACKAGE DIMENSIONS
(Unit: mm)
QFP64-P-1414-0.80-BK
Mirror finish
5
Notes for Mounting the Surface Mount Type Package
Package material Epoxy resin Lead frame material 42 alloy Pin treatment Solder plating ( 5m) Package weight (g) 0.87 TYP. Rev. No./Last Revised 6/Feb. 23, 2001
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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REVISION HISTORY
Document No. FEDL9810BFULL-01 FEDL9810BFULL-02 FEDL9810BFULL-03 Page Date Jun. 2000 May. 2001 Jun 20, 2003 7,20,32,33 7,20,32,33 Previous Edition - - Current Edition - - Edition 1 Edition 2 Corrected the output impedance of analog Description
signals.
Corrected the word "AOUT" to "LDAO,RDAO" In Analog Characteristics table.
7
7
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NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2003 Oki Electric Industry Co., Ltd.
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